PCIe 6.0 specifications at final version: 128 Gb / s
PCI-SIG announced this week that the PCIe 6.0 specification has reached its final draft status, which is a milestone that officially marks the completion of development. All systems-on-a-chip conforming to the PCIe 6.0 version 0.9 specification will conform to the final version 1.0 of the technology. The only question is which applications will actually have to adopt PCIe Gen6.
PCIe Gen6 will increase the data transfer rate to 64 GT / s per pin, compared to 32 GT / s for PCIe Gen5 and 16 GT / s for PCIe Gen4, but will maintain backward compatibility with existing hardware. The new technology allows data transfer of up to 128 GB per second in each direction via an x16 interface.
PCI Express specifications have five main checkpoints: Concept, First Draft, Full Draft, Final Draft, and Final Draft. The release of the PCIe 6.0 Complete Draft (version 0.7) specification just under a year ago has allowed large companies as well as developers of technologies like Synopsys to start implementing the IP and PHY of their controller. PCIe 6.0 in silicon. The publication of the PCIe 6.0 Final Draft (version 0.9) specification marks a point after which no functional changes are allowed and PCI-SIG members should start reviewing the standard for their intellectual property and patents.
Companies that have successfully built support for PCIe 6.0 v0.9 into their systems-on-chips (SoCs) can theoretically start selling them as “PCIe 6.0 Ready”, but they won’t be able to confirm. officially compliance with the final version of PCIe 6.0. 1.0 because there is currently no formal PCIe 6.0 compliance program and no PCIe 6.0 compliance workshop is taking place.
To make such extreme data transfer rates and bandwidth possible, the developers of the new standard must adopt four-level pulse amplitude modulation (PAM-4) of signaling, which is also used for technologies. high-end network like InfiniBand as well as GDDR6X memory. Additionally, PCIe Gen6 features low latency forward error correction (FEC) to ensure high efficiency at high data rates.
While PCIe 6.0 is a big step forward for the interface as it brings many innovations and dramatically increases performance, it will also present many challenges for chip and system designers. First of all, PAM-4 is always expensive in terms of power and chip size, which is why it has not been widely adopted beyond the high-end 100 GbE and 200 GbE data center standards. or corporate networks. Second, 64 GT / s is a very high data transfer rate and while PAM-4 with FEC will help alleviate some of the difficulties, signal transmission on printed circuit boards (PCBs) will need to be optimized for crosstalk, the loss, reflections, and integrity of the diet.
Essentially, this means that not all SoC designers (especially in the client PC space) will be eager to adopt PCIe 6.0 due to cost and power issues. Additionally, implementing PCIe 6.0 at the system level will require complex PCBs and the frequent use of expensive resynchronizations and reddrivers over relatively short distances. Overall, while PCIe 6.0 makes a lot of sense for specialized servers and systems, it can be too expensive for extensive use on client PCs, so consumer grade GPUs and SSD controllers can latch on. ‘adopt.